Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. These dynamic random access memory circuits frequently utilize memory cells formed by a single access transistor and a storage capacitor for storing an electrical charge representing a datum. An increasing demand for greater cell density in dynamic random access memory circuits has been fulfilled by reducing the operating voltage and the feature sizes of both the access transistor and the storage capacitor. These reductions in operating voltage and feature sizes of the storage capacitor reduce total charge that may be stored in the memory cell. The reduction in access transistor feature sizes, however, decreases the access transistor threshold voltage and increases subthreshold conduction. Moreover, this increase in subthreshold conduction increases the rate at which charge stored on the storage capacitor leaks through the access transistor.
Previous memory circuits have employed row decoders with level translators as disclosed in U.S. Pat. application Ser. No. 08/339,308, filed TI-16660B. The row decoder, disclosed in FIG. 7 of that application, uses a level translator to increase the word line voltage and avoid a threshold voltage loss at the storage capacitor due to the access transistor. Another embodiment disclosed in FIG. 8 uses a level translator in the word line drive circuit to accomplish a similar purpose. However, both embodiments drive the word line voltage to reference voltage V.sub.SS to turn off the access transistor. Thus, the rate of charge leakage from the storage capacitor may still be unacceptable due to the subthreshold characteristics of the access transistor.